RIPPLE COUNTER

A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop. Asynchronous counters are also called ripple-counters because of the way the clock pulse ripples it way through the flip-flops.

The MOD of the ripple counter or asynchronous counter is 2ⁿ if n flip-flops are used. For a 4-bit counter, the range of the count is 0000 to 1111 (2⁴-1). A counter may count up or count down or count up and down depending on the input control. The count sequence usually repeats itself. When counting up, the count sequence goes from 0000, 0001, 0010, … 1110 , 1111 , 0000, 0001, … etc. When counting down the count sequence goes in the opposite manner: 1111, 1110, … 0010, 0001, 0000, 1111, 1110, … etc.

The complement of the count sequence counts in reverse direction. If the uncomplemented output counts up, the complemented output counts down. If the uncomplemented output counts down, the complemented output counts up.

There are many ways to implement the ripple counter depending on the characteristics of the flip flops used and the requirements of the count sequence.

• Clock Trigger: Positive edged or Negative edged
• JK or D flip-flops
• Count Direction: Up, Down, or Up/Down

Asynchronous counters are slower than synchronous counters because of the delay in the transmission of the pulses from flip-flop to flip-flop. With a synchronous circuit, all the bits in the count change synchronously with the assertion of the clock. Examples of synchronous counters are the Ring and Johnson counter.

It can be implemented using D-type flip-flops or JK-type flip-flops.

The circuit below uses 2 D flip-flops to implement a divide-by-4 ripple counter (2ⁿ = 2² = 4). It counts down.

SEQUENCE DETECTORS

Sequence detection is the act of recognizing a predefined series of inputs. In our case, we are looking for very simple things very slowly. We are looking for a series of ones and zeros similar to 1011. The overwhelming beauty of programmable logic is its ability to work with DSP (digital signal processing). The capability of processing a great deal of information quickly can not be overemphasized. Suppose you were working at the VLA in Socorro and you wanted to scan thousands of bits of digital information looking for a series of bits that represents an RF signal from a distant galaxy. Or, suppose you wanted to scan a digital image of a human lung looking for a digital signature that could represent a cancerous cell. These are very broad interpretations.

                SYNCHRONOUS COUNTER

A 4-bit synchronous counter using JK flip-flops

In synchronous counters, the clock inputs of all the flip-flops are connected together and are triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in parallel). The circuit below is a 4-bit synchronous counter. The J and K inputs of FF0 are connected to HIGH. FF1 has its J and K inputs connected to the output of FF0, and the J and K inputs of FF2 are connected to the output of an AND gate that is fed by the outputs of FF0 and FF1. A simple way of implementing the logic for each bit of an ascending counter (which is what is depicted in the adjacent image) is for each bit to toggle when all of the less significant bits are at a logic high state.

Synchronous counters can also be implemented with hardware finite-state machines, which are more complex but allow for smoother, more stable transitions.